Makefile

Introduction

If you run make the make program will look for a file named Makefile in your directory, and then execute it.
If you have several makefiles, then you can execute them with the command make -f MyMakefile

The basic makefile is composed of:
target: dependencies
[tab] system command

Example1
all:
g++ main.cpp hello.cpp factorial.cpp -o hello

In Example1 the target is called all. Also there are no dependencies, so make safely executes the system commands specified. Finally, make compiles the program according to the command line we gave it.

Using Dependencies

make creates programs according to the file dependencies. Sometimes is useful to use different targets. This is because if you modify a single file in your project, you don't have to recompile everything, only what you modified.

Example 2
all: hello
hello: main.o factorial.o hello.o
g++ main.o factorial.o hello.o -o hello

main.o: main.cpp
g++ -c main.cpp

factorial.o: factorial.cpp
g++ -c factorial.cpp

hello.o: hello.cpp
g++ -c hello.cpp

clean:
rm -rf *o hello

Using Macros and comments

The make program allows you to use macros, which are similar to variables, to store names of files. This is useful in situations where you want to change the compiler, or the compiler options.
Comments can be placed in a Makefile by placing a pound sign (#) in front of it.

Example 3
#the variable CC will be the compiler to use.
CC=g++
#CFLAGS will be the options passed to the compiler.
CFLAGS=-c -Wall

To use macros just assign a value to a macro before you start to write your targets. After that, you can just use them with the dereference operator $(VAR).

Special Macros

In addition to those macros which you can create yourself, there are a few macros which are used internally by the make program. Here are some of those, listed below:

CC Contains the current C compiler. Defaults to cc.
CFLAGS Special options which are added to the built-in C rule. (See next page.)
$@ Full name of the current target.
$? A list of files for current dependency which are out-of-date.
$< The source file of the current (single) dependency.

Example 4
OBJS = data.o io.o main.o

  1. using the following within the Makefile substitutes .o at the end with .c, giving you the following result: data.c io.c main.c

$(OBJS:.o=.c)

Predefined rules

make knows already that in order to create a .o file, it must use cc -c on the corresponding .c file. These rules are built into make, and you can take advantage of this to shorten your Makefile.
OBJECTS = data.o main.o io.o
project1: $(OBJECTS)
cc $(OBJECTS) -o project1
data.o: data.h
main.o: data.h io.h
io.o: io.h

Special dependencies

Special form of the dependency, where the action specified can differ, depending on which file has changed.

Example 5
target :: source1
command1
target :: source2
command2

If source1 changes, target is created or updated using command1; command2 is used if source2 is modified instead.

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